A low-power, high-gain circuit for function electrical stimulation （FES） is designed for the microelectronic neural signal regeneration system based on CSMC （CSMC Technologies Corporation） 0. 6μm CMOS （complementary metal-oxide-semiconductor transistor） technology. It can be used to stimulate microelectrodes connected with the nerve bundles to regenerate neural signals. This circuit consists of two stages： a full differential folded-cascode amplifier input stage and a complementary class-AB output stage with an overload protection circuit. The rail-to-rail input and output stages are used to ensure a wide range of input and output voltages. The simulation results show that the gain of the circuit is 81 dB; the 3 dB-bandwidth is 295 kHz. The chip occupies a die area of 1.06 mm × 0. 52 mm. The on-wafer measurement results show that under a single supply voltage of ＋ 5 V, the DC power consumption is about 7. 5 mW and the output voltage amplitude is 4. 8 V. The chip can also mn well under single supply voltage of ＋ 3.3 V.
