A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.
为提高CMOS集成电路中电流基准的精度和稳定性，提出了一种结构简单，电源抑制比（PSRR）很高的电流基准结构——三支路电流基准．应用基尔霍夫定律（Kirchhoff’s current and voltage law，Kcl Kvl）和偏微分方程，对比分析了传统的电流基准、共源共栅电流基准以及三支路电流基准的小信号模型，求解出了这3种电路的电源抑制比公式．对比发现传统电流基准和共源共栅电流基准的节点电压正反馈限制了电流基准的性能，三支路结构由于节点电压成强负反馈，拥有更高的PSRR．三支路电流基准采用了一阶温度补偿方案，保证了温度稳定性．经CSMC0．5μm工艺仿真结果显示，三支路基准在输入电压1．5～5．0V的低频PSRR达-77．9dB，明显优于另外两种结构；在～20～120℃温度区间内输出电流稳定性达到了255×10^-6／℃，满足了大多数应用的要求．
