A sensitivity design method for a CMOS optoelectronic integrated circuit （OEIC） receiver is reported. The receiver consists of a regulated cascade （RGC） transimpedance amplifier （TIA） and a double photodiode （DPD） detector. The noise and sensitivity of the receiver are analyzed in detail. The noise mainly comes from the thermal noise of resistors and the flicker noise of MOSFETs. The relationship between noise and receiver sensitivity is presented. The sensitivity design method for the receiver is given by a set of equations. The OEIC receiver was implemented in a CSMC 0.6μm standard CMOS process. The measured eye diagram shows that the CMOS OEIC receiver is able to work at bit rates of up to 1.25GB/s and the sensitivity is - 12dBm.
The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit （OEIC） receiver are reported. Each channel of the receiver consists of a photodetector, a transimpedance amplifier,and a post-amplifier. The double photodiode structure speeds up the receiver but hinders responsivity. The adoption of active inductors in the TIA circuit extends the - 3dB bandwidth to a higher level. The receiver has been realized in a CSMC 0.6μm standard CMOS process. The measured results show that a single channel of the receiver is able to work at bit rates of 0.8- 1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s.
A wideband monolithic optoelectronic integrated receiver with a high-speed photo-detector,completely compatible with standard CMOS processes,is designed and implemented in 0.6μm standard CMOS technology.The experimental results demonstrate that its performance approaches applicable requirements,where the photo-detector achieves a -3dB frequency of 1.11GHz,and the receiver achieves a 3dB bandwidth of 733MHz and a sensitivity of -9dBm for λ=850nm at BER=10-12.
