We have investigated the temperature dependent interfacial and electrical characteristics of p-GaAs metal-oxide-semiconductor capacitors during atomic layer deposition （ALD） and annealing of HfO2 using the tetrakis （ethylmethyl） amino hafnium precursor. The leakage current decreases with the increase of the ALD tem- perature and the lowest current is obtained at 300 ℃ as a result of the Frenkel-Poole conduction induced leakage current being greatly weakened by the reduction of interfacial oxides at the higher temperature. Post deposition annealing （PDA） at 500 ℃ after ALD at 300 ℃ leads to the lowest leakage current compared with other annealing temperatures. A pronounced reduction in As oxides during PDA at 500 ℃ has been observed using X-ray pho- toelectron spectroscopy at the interface resulting in a proportional increase in Ga203. The increment of Ga203 after PDA depends on the amount of residual As oxides after ALD. Thus, the ALD temperature plays an important role in determining the high-k/GaAs interface condition. Meanwhile, an optimum PDA temperature is essential for obtaining good dielectric properties.
There is a great interest in monolithic 4H-SiC Junction Barrier Schottky （JBS） diodes with the capability of a high forward current for industrial power applications. In this paper, we report large-area monolithic 4H-SiC JBS diodes fabricated on a 10 μm 4H-SiC epitaxial layer doped to 6×1015 cm-3. JBS diodes with an active area of 30 mm2 had a forward current of up to 330 A at a forward voltage of 5 V, which corresponds to a current density of 1100 A/cm2. A near ideal breakdown voltage of 1.6 kV was also achieved for a reverse current of up to 100 gA through the use of an optimum multiple floating guard rings （MFGR） termination, which is about 87.2% of the theoretical value. The differential specific-on resistance （RSP-ON） was meas- ured to be 3.3 mΩcm2, leading to a FOM （VB2/RSP-ON） value of 0.78 GW/cm2, which is very close to the theoretical limit of the tradeoff between the specific-on resistance and breakdown voltage for 4H-SiC unipolar devices.
In this paper, the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors （MOSF- FETs） have been fabricated and characterized. A sandwich- （nitridation-oxidation-nitridation） type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H-SiC/SiO2 were examined by the measurement of HF l-V, G-V, and C-V over a range of frequencies. The ideal C-V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H-SiC was reduced to 2 x 1011 eV-l.cm-2, the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak field- effect mobility is about 32.5 cm2.V-1 .s-1, and the maximum peak field-effect mobility of 38 cm2-V-1 .s-1 was achieved in fabricated lateral 4H-SiC MOSFFETs.
In this paper, 1.2 kV, 3.3 kV, and 5.0 kV class 4H-SiC power Schottky barrier diodes （SBDs） are fabricated with three N-type drift layer thickness values of 10 μm, 30μm, and 50 μm, respectively. The avalanche breakdown capabilities, static and transient characteristics of the fabricated devices are measured in detail and compared with the theoretical pre- dictions. It is found that the experimental results match well with the theoretical calculation results and are very close to the 4H-SiC theoretical limit line. The best achieved breakdown voltages （BVs） of the diodes on the 10 p.m, 30 m, and 50 -tm epilayers are 1400 V, 3320 V, and 5200 V, respectively. Differential specific-on resistances （Ron-sp） are 2.1 m--cm2, 7.34 mO. cm2, and 30.3 m-. cm2, respectively.
Atomic layer deposited （ALD） Al2O3/dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8° off-axis 4H-SiC （0001） epitaxial wafers are investigated in this paper. The metal-insulation-semiconductor （MIS） capacitors, respectively with different gate dielectric stacks （Al2O3/SiO2, Al2O3, and SiO2） are fabricated and compared with each other. The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field （≥12 MV/cm） comparable to SiO2, and a relatively low gate leakage current of 1 × 10-7 A/cm2 at an electric field of 4 MV/cm comparable to Al2O3. The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage, indicating a less effective charge and slow-trap density near the interface.
Multiple-energy aluminium （AI＋） implantation into 4H-SiC （0001） epilayer and activation anneal with a graphite encapsnlation layer were investigated in this paper. Measurements showed that the implanted Ak＋ box doping profile was formed and a high ion activation ratio of 78% was achieved by 40 rain annealing at 1600℃ using a horizontal chemical vapor deposition （CVD） reactor. The step bunching effect associated with the high temper：lture post implantation activation annealing （PIA） process was dramatically suppressed by using the graphite encapsulation layer. And a flat and smooth surface with a small average surface roughness （RMS） value of around 1.16 nm was achieved for the implanted 4H-SiC after the PIA process. It was demonstrated that this surface protection technique is a quite effective process for 4H-SiC power devices fabrication.
