Atomic layer deposited （ALD） Al2O3/dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8° off-axis 4H-SiC （0001） epitaxial wafers are investigated in this paper. The metal-insulation-semiconductor （MIS） capacitors, respectively with different gate dielectric stacks （Al2O3/SiO2, Al2O3, and SiO2） are fabricated and compared with each other. The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field （≥12 MV/cm） comparable to SiO2, and a relatively low gate leakage current of 1 × 10-7 A/cm2 at an electric field of 4 MV/cm comparable to Al2O3. The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage, indicating a less effective charge and slow-trap density near the interface.
Multiple-energy aluminium （AI＋） implantation into 4H-SiC （0001） epilayer and activation anneal with a graphite encapsnlation layer were investigated in this paper. Measurements showed that the implanted Ak＋ box doping profile was formed and a high ion activation ratio of 78% was achieved by 40 rain annealing at 1600℃ using a horizontal chemical vapor deposition （CVD） reactor. The step bunching effect associated with the high temper：lture post implantation activation annealing （PIA） process was dramatically suppressed by using the graphite encapsulation layer. And a flat and smooth surface with a small average surface roughness （RMS） value of around 1.16 nm was achieved for the implanted 4H-SiC after the PIA process. It was demonstrated that this surface protection technique is a quite effective process for 4H-SiC power devices fabrication.
