In this paper,a 2-mm long on-chip dipole antenna pair on silicon substrate is simulated to investigate the transmission characteristics.A novel technique is proposed by employing a 0.35-mm thick diamond layer between silicon substrate and heat sink to improve antenna performance.The simulated transmission gain of this antenna pair with 1 mm separation on a 10-Ω cm silicon substrate increases by 9 dB at 20 GHz.A modified plane wave model involving diamond layer is also presented to explain gain improvement.Effects of dielectric variety,diamond thickness,substrate resistivity and antenna pair separation on transmission gain have been studied.The results indicate that thinner diamond layer along with high resistivity substrate is preferred.Our method makes integrated dipole antennas well suitable for intra-chip wireless interconnection which is known as a future solution to replace critical wiring interconnection.
This paper describes a low-noise phase-locked loop （PLL） design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18 μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.
