Single event effects(SEEs) induced by radiations become a significant challenge to the reliability for modern electronic systems. To evaluate SEEs susceptibility for microelectronic devices and integrated circuits(ICs), an SEE testing system with flexibility and robustness was developed at Heavy Ion Research Facility in Lanzhou(HIRFL). The system is compatible with various types of microelectronic devices and ICs, and supports plenty of complex and high-speed test schemes and plans for the irradiated devices under test(DUTs). Thanks to the combination of meticulous circuit design and the hardened logic design, the system has additional performances to avoid an overheated situation and irradiations by stray radiations. The system has been tested and verified by experiments for irradiating devices at HIRFL.
Gamma Ray Array Detector(GRAD) is one of external target facility subsystems in the Cooling Storage Ring on the Heavy Ion Research Facility at Lanzhou(HIRFL-CSR).The trigger subsystem of GRAD is required to make a fast L1 trigger decision with a fixed latency for the data acquisition.Because the hit signals from the detector are asynchronous with the local clock of the trigger system,a nondeterministic latency(the value changes between zero and one clock period) is generated when the synchronous receivers of the conventional trigger system process the hit signals.In this paper,an improved trigger logic based on a field-programmable gate array is developed,and comprised of zero-delay broadening circuits as receivers and an improved adding circuit designed for the new receivers.Software simulation and experimental measurement have been conducted.Comparison with the conventional trigger logic,the improved trigger logic has the advantage of eliminating the nondeterministic latency and reducing the total processing latency.
A single width NIM module that includes eight channels of the time-to-amplitude converter （TAC） and the charge-to-amplitude converter （QAC） is introduced in the paper, which is designed for the large neutron wall detector to measure charge （energy） and time interval simultaneously. The module adopts a high precision gated integration circuit to realize TAC and QAC. ：The input range of TAC is from 30 ns to 1 μs, and the input range of QAC is from 40 pC to 600 pC. The linearity error of TAC is lower than 1.28%, and the time resolution of TAC is less than 0.871%. The linearity error of QAC is lower than 0.81%, and the resolution of QAC is better than 0.936%.
A readout electronics has been developed for the silicon strip array detector system of HIRFL-CSR-ETF.It consists of 48 front end electronics(FEE)boards,12 PXI-DAQ boards and one trigger board.It can implement energy and time measurements of 4608 channels.Each FEE board is based on 6 ASICs(ATHED),which implements energy and time measurements of 96 channels.The PXI-DAQ board meets requirements of high-speed counting and amount of readout channels and can process signals of 4 FEEs.The trigger board is developed to select the valid events.The energy linearity of the readout electronics is better than 0.3%in the dynamic range of 0.1-0.7V.In the test with a standard triple alpha source,the energy resolution was 1.8%at 5.48 MeV.This readout electronics enables the silicon strip array system to identify particles of A<14.
Embedded RAM blocks（BRAMs） in field programmable gate arrays（FPGAs） are susceptible to single event effects（SEEs） induced by environmental factors such as cosmic rays, heavy ions, alpha particles and so on. As technology scales, the issue will be more serious. In order to tackle this issue, two different error correcting codes（ECCs）, the shortened Hamming codes and shortened BCH codes, are investigated in this paper. The concrete design methods of the codes are presented. Also, the codes are both implemented in flash-based FPGAs. Finally, the synthesis report and simulation results are presented in the paper. Moreover, heavy-ion experiments are performed,and the experimental results indicate that the error cross-section of the device using the shortened Hamming codes can be reduced by two orders of magnitude compared with the device without mitigation, and no errors are discovered in the experiments for the device using the shortened BCH codes.
